1. Field of the Invention
The present invention is generally in the field of semiconductors. More particularly, the invention is in the field of semiconductor transistors.
2. Background Art
In conventional implementations, a transistor, such as a conventional Field Effect Transistor (FET), may include a heavily doped polysilicon gate structure over a gate oxide, which forms a dielectric barrier between the gate structure and the substrate.
As the transistors utilized in core and input/output (IO) sections of devices have been scaled down to smaller dimensions in advanced process technologies, however, their operating voltages have been reduced as well. Consequently, it has become increasingly difficult to interface these scaled down transistors with the higher voltage operating devices with which they may still need to be compatible. Attempting to utilize conventional circuit design techniques to interface these reduced operating voltage transistors with higher voltage devices can result in problems such as accelerated Time Dependent Dielectric Breakdown (TDDB), for example. As a result, when used with higher voltage devices, the operational lifetimes of those scaled down transistors may fail to meet the desired durability specifications.
One conventional approach to resolving the problems described, requires separate design of circuits utilizing these scaled down transistors in combination with higher voltage devices. Unfortunately this approach tends to be inefficient and time consuming. Another conventional solution requires the addition of processing steps to existing transistor fabrication process flows, an approach that can substantially increase the cost of fabrication while reducing manufacturing throughput.